The present invention generally relates to a sample and hold circuit, and more particularly, a sample and hold circuit having low distortion at a large full power bandwidth.
Typically, a sample and hold circuit has an output which is proportional to the input until a "hold" signal is received. Upon receipt of that signal, the amplifier output is maintained essentially constant even though there may be changes in the input signal.
As shown in FIG. 1, the conceptual design of an integrating sample and hold circuit (Harris part no. HA5320, HA5330 U.S. Pat. No. 4,636,744) comprises a first independent amplifier 1, hereinafter sometimes referred to as the transconductance stage, and a second independent amplifier 2, having a high input impedance, these amplifiers 1, 2 being respectively connected by a sampling switch S.sub.1. The transconductance stage provides an output current or slew current I.sub.S which is equal to the transconductance of the first independent amplifier 1 times the voltage of the input signal thereto With sampling switch S.sub.1 closed, a hold capacitor C.sub.H, connected at respective ends to the input and output terminals of the second amplifier 2, is charged by the slew current I.sub.S when an input signal is applied to the input of the first amplifier 1.
Upon receipt of the "hold" command, the sampling switch S.sub.1 is opened, thus leaving the hold capacitor C.sub.H charged at the instantaneous value of the input signal. Capacitor C.sub.H is not discharged because the second amplifier 2 has a high input impedance so that the output of the second amplifier 2 remains essentially steady for a period of time. The "hold" signal may be generated by an external circuit (coupled to a process or experiment) or by a computer or digital control unit under control of the storage program.
The integrating type sample and hold circuitry illustrated in FIG. 1 is advantageous due to the switch stage operating at virtual ground. This allows for a charge injection compensation, leakage cancellation, signal independent pedestal error and the like. The hold capacitor C.sub.H must be large in order to store charge to accomplish the sample and hold function and unfortunately, the hold capacitor C.sub.H must be slewed by the transconductance stage under large signal conditions. This is disadvantageous because to achieve a large full power bandwidth of, for example, 500 kHz, along with a sizable hold capacitor C.sub.H, the front end slewing current I.sub.S must be unreasonably large.
Assume a full power bandwidth (FPBW) defined as as follows: ##EQU1## wherein SR=the slew rate, V.sub.a =sine wave amplitude and the slew rate is the same as the droop rate. Thus, for a full power bandwidth of 500 kHz at low distortion, the slew rate must be even greater than what is assumed above and thus the slew current would also be even greater.
For the sake of discussion, assume a factor of 2.0 slew rate advantage. Thus, the slew rate minimum is 500 Hzk.times.2.times..pi. which equals 31.4 V/uS and for low distortion use 2.0.times.31.4 V/microseconds which equals 62.8 V/microseconds. Assuming a hold capacitance of 110 pf, the parasitic capacitance of 10 pf gives a total slew capacitance of 120 pf. The slew current necessary is thus: EQU I.sub.slew =62.8 V/microseconds.times.120 pf=7.52 mA.
This is a very large current value to bias a differential pair on a circuit with a total current supply in the 10 mA range.
Therefore, it is an object of the present invention to eliminate the need to drive the hold capacitor of an integrating type sample and hold circuit with the slew current provided at an output of a transductance stage of the sample and hold circuit.
It is a further object of the present invention to eliminate the need for any distortion producing slew enhancement stages to provide a good full power bandwidth with low distortion.
It is yet another object of the present invention to provide a sample and hold circuit in which the front end is biased at a more reasonable current and a greater full power bandwidth is achieved.
These and other objects are provided, in accordance with preferred embodiments of the present invention, by a sample and hold circuit having low distortion at a large full power bandwidth, the circuit comprising an input stage having at least an input for receiving a signal to be sampled and an output for providing an output signal representative of an instantaneous value of the signal to be sampled. Connected via a sampling switch to the output of the input stage is an output stage having a compensation capacitor which is driven by the output signal, i.e. slew current I.sub.S, of the input stage. The compensation capacitor has a charge value or voltage representative of the instantaneous value of the output signal of the input stage, the compensation capacitor being connected across the input and output of the output stage. A hold capacitor is also included and arranged in parallel with the compensation capacitor. The hold capacitor has a capacitance much larger than that of the compensation capacitor and a voltage equal to voltage of the compensation capacitor. A switchable voltage buffer for isolating the hold capacitor from the output of the input stage and for driving the hold capacitor to a voltage value equaling the voltage of the compensation capacitor is also provided, the voltage buffer deriving its current independently from the slew current I.sub.S.
This arrangement combines the advantages of an integrating type sample of hold circuit with the advantages of a buffer type sample of hold circuit. In that one of the major disadvantages of the integrating type of sample and hold circuit is that the hold capacitor also doubles as the compensation capacitor, preferred embodiments of the present invention avoid the need to drive the hold capacitor with the transductance stage slew current I.sub.S by buffering the hold capacitor with a voltage buffer and providing a compensation capacitor, with a small capacitance which is slewed by the slew current I.sub.S of the transconductance stage so as to greatly reduce the slew current requirements. This arrangement allows the compensation capacitor to be made as small as possible for bandwidth needs and the hold capacitor as large as needed for the sample and hold requirements. Thus, the hold capacitor is driven by a voltage provided by the voltage buffer and not the slew current I.sub.S and therefore slewing does not occur at the hold capacitor but only at the smaller compensation capacitor.
This arrangement further provides the advantage that, because the compensation capacitor can be much smaller than the hold capacitor, the slew current I.sub.S needed to drive the compensation capacitor is reduced. Moreover, there is an elimination of the need for any distortion producing slew enhancement stages and a good full power bandwidth is achieve with lower power.
Thus, the performance improvements provided by preferred embodiments of the present invention include a reduction in the power requirements for achieving a given large power bandwidth, a greater full power and small signal bandwidth as well as improved hold characteristics resulting from a large hold capacitor. As a result, increasing the hold capacitor no longer causes bandwidth and speed trade-offs, specifically, lower drop rate, lower pedestal error, as well as lower drift current requirements. Further, low distortion is provided because no slew enhancement circuit or parallel circuits are needed to achieve the high slew rate and high full power bandwidth, and improved acquisition time is achieved resulting from the high slew rate and high power bandwidth combination.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.